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1 ? fn9010.2 isl6402a 1.4mhz dual, 180 out-of-phase, step- down pwm and single linear controller the isl6402a is a high-perform ance, triple-output controller optimized for converting wall adapter, battery or network intermediate bus dc input supp lies into the system supply voltages required for a wide variety of applications. each output is adjustable down to 0.8v. the two pwms are synchronized 180 o out of phase reducing the rms input current and ripple voltage. the isl6402a incorporates seve ral protection features. an adjustable overcurrent protection circuit monitors the output current by sensing the voltage drop across the lower mosfet. hiccup mode overcurr ent operation protects the dc-dc components from damage during output overload/short circuit conditions. each pwm has an independent logic-level shutdown input (sd1 and sd2). a single pgood signal is issued when soft-start is complete on both pwm controllers and their outputs are within 10% of the set point and the linear regu lator output is greater than 75% of its setpoint. thermal shutdown circuitry turns off the device if the junction temperature exceeds +150c. features ? wide input supply voltage range . . . . . . . . . 4.5v to 24v ? three independently prog rammable output voltages ? switching frequency . . . . . . . . . . . . . . . . . . . . . . .1.4mhz ? out of phase pwm controller operation - reduces required input capacitance and power supply induced loads ? no external current sense resistor - uses lower mosfet?s r ds(on) ? bi-directional frequency synchronization for synchronizing multiple isl6402as ? programmable soft-start ? extensive circuit protection functions - pgood -uvlo - overcurrent - overtemperature - independent shutdown for both pwms ? excellent dynamic response - voltage feed-forward with current mode control ? tssop and qfn packages: - qfn - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile ? pb-free available as an option applications ? power supplies with multiple outputs ? xdsl modems/routers ? dsp, asic, and fpga power supplies ? set-top boxes ? dual output supplies for dsp, memory, logic, p core and i/o ? telecom systems ordering information part number temp. range (c) package pkg. dwg. # isl6402air -40 to 85 28 ld qfn l28.5x5 isl6402air-t 28 ld qfn tape and reel l28.5x5 isl6402air-tk 28 ld qfn tape and reel l28.5x5 isl6402airz (see note) -40 to 85 28 ld qfn (pb-free) l28.5x5 isl6402airz-t (see note) 28 ld qfn tape and reel (pb-free) l28.5x5 isl6402aiv -40 to 85 28 ld tssop m28.173 ISL6402AIV-T 28 ld tssop tape and reel m28.173 isl6402aivz (see note) -40 to 85 28 ld tssop (pb-free) m28.173 isl6402aivz-t (see note) 28 ld tssop tape and reel (pb-free) m28.173 note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. data sheet july 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 pinouts isl6402a (tssop) top view isl6402a (qfn) top view lgate2 boot2 ugate2 phase2 isen2 pgood vcc_5v sd2 ss2 ocset2 fb2 vin sync lgate1 ugate1 phase1 isen1 pgnd ss1 ocset1 fb1 sgnd gate3 fb3 boot1 sd1 sgnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 sgnd phase2 isen2 pgood vcc_5v sd2 ss2 ocset2 isen1 pgnd sd1 ss1 sgnd ocset1 fb1 fb2 sgnd vin sync fb3 sgnd gate3 ugate2 boot2 lgate2 lgate1 boot1 phase1 ugate1 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 isl6402a
3 block diagram pgood output voltage monitor + - ref + - oc logic ss1 s q r pwm1 latch boot1 ugate1 phase1 lgate1 lgdr hgdr hi lo gate logic pwm shutdown gate3 linear controller ref fb3 clock ramp sync vin ldo & sgnd por + - isen1 fb1 ocset1 clk power-on reset (por) vcc_5v pgnd + - + - oc comp clk sd1 sd1 + - ref + - oc logic ss2 s q r pwm2 latch boot2 ugate2 phase2 lgate2 lgdr hgdr hi lo gate logic pwm shutdown + - isen2 fb2 ocset2 + - + - oc comp clk sd2 sd2 fb1 fb2 pwm1 pwm2 fb3 vcc_5v vcc_5v ss1 ss2 +5v ss2 ss1 + + - - isl6402a
4 typical application schematic + pgood +12v ugate2 phase2 isl6402a + c1 r5 c10 23 26 4 28 6 18 16 lgate2 q2b 19 14 isen2 r4 21 c8 boot2 vin 5 d2 25 17 c5 r6 9 27 gate3 ocset2 fb1 ugate1 phase1 + c9 pgnd lgate1 q1b isen1 r3 c7 boot1 d1 r2 sync ocset1 vcc_5v 7 10 r10 8 sd2 24 1 3 2 13 l2 fb3 15 ss1 ss2 11 sgnd 20 c3 q1a vout1 r1 q1a fb2 sgnd vout2 q3 + r12 r13 c12 vout3 sd1 r7 +2.5v +3.3v +3.3v c2 c6 l1 c4 +1.2v (see note) 22 r11 c11 note: pin numbers correspond to the tssop pinout. r8 sgnd 12 vcc_5v v r9 vout2 isl6402a
5 absolute maximum rati ngs thermal information supply voltage (vcc_5v pin) . . . . . . . . . . . . . . . . . . . . -0.3v to +7v input voltage (vin pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+30v boot1, 2 and ugate1, 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . +35v phase1, 2 and isen1, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . +30v boot1, 2 with respect to phase1, 2 . . . . . . . . . . . . . . . . . . . +6.5v ugate1, 2. . . . . . . . . . . . (phase1, 2 - 0.3v) to (boot1, 2 +0.3v) thermal resistance (typical) ja (c/w) jc (c/w) 28 lead tssop (note 1) . . . . . . . . . . . 75 na 28 lead qfn (note 2) . . . . . . . . . . . . . 33 4 maximum junction temperature (plastic package) . -55c to 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (tssop - lead tips only) temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to 85c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 2. jc is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fea tures. for ja the ?case temp? location is the center of the exposed me tal pad on the underside of the package. see tech brief tb379. electrical specifications recommended operating conditions unles s otherwise noted. refer to block diagram and typical application schematic. v in = 5.6v to 24v, or vcc_5v = 5v 10%, t a = -40c to 85c (note 3), typical values are at t a = 25c parameter test conditions min typ max units vin supply input voltage range 5.6 12 24 v vcc_5v supply (note 4) input voltage 4.5 5.0 5.6 v output voltage v in > 5.6v, i l = 20ma 4.5 5.0 5.5 v maximum output current v in = 12v 60 - - ma supply current shutdown current (note 5) sd1 = sd2 = gnd - 50 375 a operating current (note 6) - 2.0 4.0 ma reference section nominal reference voltage - 0.8 - v reference voltage tolerance -1.0 - 1.0 % power-on reset rising vcc_5v threshold 4.25 4.45 4.5 v falling vcc_5v threshold 3.95 4.2 4.4 v oscillator total frequency variation 1.25 1.4 1.5 mhz peak-to-peak sawtooth amplitude (note 7) v in = 12v - 1.5 - v v in = 5v - 0.625 - v ramp offset (note 8) -1.0- v sync input rise/fall time - - 10.0 ns sync frequency range 5.1 5.6 6.0 mhz sync input high level 3.5 - - v sync input low level --1.5v sync input minimum pulse width 10 - - ns sync output high level vcc - 0.6v - - v isl6402a
6 shutdown1/shutdown2 high level (converter e nabled) internal pull-up (3 a) 2.0 - - v low level (converter disabled) - - 0.8 v pwm converters output voltage 0.8 - - v fb pin bias current --100na maximum duty cycle pwm1 71 - - % pwm2 73 - - % minimum duty cycle -4-% pwm controller error amplifiers dc gain (note 8) 80 88 - db gain-bandwidth product (note 8) 5.9 - - mhz slew rate (note 8) -2.0-v/ s maximum output voltage (note 8) 0.9 - - v minimum output voltage (note 8) - - 3.6 v pwm controller gate drivers (note 9) sink/source current - 400 - ma upper drive pull-up resistance vcc_5v = 4.5v - 8 - upper drive pull-down resistance vcc_5v = 4.5v - 3.2 - lower drive pull-up resistance vcc_5v = 4.5v - 8 - lower drive pull-down resistance vcc_5v = 4.5v - 1.8 - rise time c out = 1000pf - 18 - ns fall time c out = 1000pf - 18 - ns linear controller drive sink current 50 - - ma fb3 feedback threshold i = 21ma - 0.8 - v undervoltage threshold v fb -75- % fb3 input leakage current (note 8) - - 45 na amplifier transconductance v fb = 0.8v, i = 21ma - 2 - a/v power good and control functions pgood low level voltage pull-up = 100k ? -0.10.5v pgood leakage current - - 1.0 a pgood upper threshold, pwm 1 and 2 fraction of set point 105 - 120 % pgood lower threshold, pwm 1 and 2 fraction of set point 80 - 95 % pgood for linear controller 70 75 80 % electrical specifications recommended operating conditions unles s otherwise noted. refer to block diagram and typical application schematic. v in = 5.6v to 24v, or vcc_5v = 5v 10%, t a = -40c to 85c (note 3), typical values are at t a = 25c (continued) parameter test conditions min typ max units isl6402a
7 isen and current limit full scale input current (note 10) - 32 - a over-current threshold (note 10) rocset = 110k ? -64- a ocset (current limit) voltage - 1.75 - v soft-start soft-start current -5- a protection thermal shutdown rising - 150 - c hysteresis - 20 - c notes: 3. specifications at -40c and 85c are guaranteed by design, not production tested. 4. in normal operation, where the device is supplied with voltage on the v in pin, the vcc_5v pin provides a 5v output capable of 60ma (min). when the vcc_5v pin is used as a 5v supply inpu t, the internal ldo regulator is disabled and the v in input pin must be connected to the vcc_5v pin. (refer to the pin descriptions section for more details.) 5. this is the total shutdown current with vin = vcc_5v = pvcc = 5v. 6. operating current is the supply current consumed when the devic e is active but not switching. it does not include gate drive current. 7. the peak-to-peak sawtooth amplitude is production tested at 12v only; at 5v this param eter is guaranteed by design. 8. guaranteed by design; not production tested. 9. not production tested; guaranteed by characterization only. 10. guaranteed by design. the full scale current of 32a is re commended for optimum current sample and hold operation. see the feedback loop compensation section below. electrical specifications recommended operating conditions unles s otherwise noted. refer to block diagram and typical application schematic. v in = 5.6v to 24v, or vcc_5v = 5v 10%, t a = -40c to 85c (note 3), typical values are at t a = 25c (continued) parameter test conditions min typ max units isl6402a
8 typical performance curves (oscilloscope plots are taken using the isl6402aeval4b ev aluation board, vin = 12v, unless otherwise noted) figure 1. pwm1 load regulation figure 2. pwm2 load regulation figure 3. reference voltage variation over temperature figure 4. soft-start waveforms with pgood figure 5. pwm1 waveforms figure 6. pwm2 waveforms 3.3 3.32 3.33 3.35 3.38 3.39 3.4 01 2.53.5 load current (a) pwm1 output voltage (v) 4.5 0.5 1.5 2 3 4 3.37 3.36 3.34 3.31 3.3 3.32 3.33 3.35 3.38 3.39 3.4 01 2.53.5 load current (a) pwm2 output voltage (v) 4.5 0.5 1.5 2 3 4 3.37 3.36 3.34 3.31 -40 -20 20 40 80 0.75 0.81 0.85 temperature (c) reference voltage (v) 0.78 0.83 0.8 0.77 0 60 0.84 0.82 0.79 0.76 pgood 5v/div v out3 2v/div v out2 2v/div v out1 2v/div v out1 20mv/div, ac coupled i l1 0.5a/div, ac coupled phase1 10v/div v out2 20mv/div, ac coupled i l2 0.5a/div, ac coupled phase2 10v/div isl6402a
9 figure 7. load transien t response vout1 (3.3v) figure 8. lo ad transient response vout2 (3.3v) figure 9. pwm soft-start waveform figure 10. overcurrent hiccup mode operation figure 11. pwm1 efficiency vs load, vin=5v, vout=3.3v f igure 12. pwm2 efficiency vs load, vin=5v, vout=3.3v typical performance curves (continued) (oscilloscope plots are taken using the isl6402aeval4b ev aluation board, vin = 12v, unless otherwise noted) v out1 200mv/div i out1 1a/div ac coupled v out1 200mv/div ac coupled i out1 1a/div vcc_5v 1v/div v out1 1v/div v out1 2v/div i l1 2a/div ss1 2v/div 70 80 100 01 2.53.5 load current (a) pwm1 efficiency (%) 0.5 1.5 2 3 4 90 70 80 100 01 2.53.5 load current (a) pwm2 efficiency (%) 0.5 1.5 2 3 4 90 isl6402a
10 pin descriptions boot2, boot1 - these pins power the upper mosfet drivers of each pwm converter. connect this pin to the junction of the bootstrap capa citor and the cathode of the bootstrap diode. the anode of the bootstrap diode is connected to the vcc_5v pin. ugate2, ugate1 - these pins provide the gate drive for the upper mosfets. phase2, phase1 - these pins are connected to the junction of the upper mosfet?s source, output filter inductor and lower mosfets drain. lgate2, lgate1 - these pins provide the gate drive for the lower mosfets. pgnd - this pin provides the power ground connection for the lower gate drivers for both pwm1 and pwm2. this pin should be connected to the sources of the lower mosfets and the (-) terminals of the external input capacitors. fb3, fb2, fb1 - these pins are connected to the feedback resistor divider and provide the voltage feedback signals for the respective controller. they set the output voltage of the converter. in addition, the pg ood circuit uses these inputs to monitor the output voltage status. isen2, isen1 - these pins are used to monitor the voltage drop across the lower mosfet for current loop feedback and overcurrent protection. pgood - this is an open drain logic output used to indicate the status of the out put voltages. this pin is pulled low when either of the two pwm outputs is not within 10% of the respective nominal voltage, or if the linear controller output is less than 75% of it?s nominal value. sgnd - (pin 20 on the tssop; pin 17 on the qfn) this is the small-signal ground, common to all 3 controllers, and must be routed separately from the high current ground (pgnd). all voltage levels are measured with respect to this pin. connect the additional sgnd pins to this pin. if using a 5v supply, connect this pin to vcc_5v. a small ceramic capacitor should be connected right next to this pin for noise decoupling. vin - use this pin to power the device with an external supply voltage with a range of 5.6v to 24v. for 5v 10% operation, connect this pin to vcc_5v. vcc_5v - this pin is the output of the internal 5v linear regulator. this output supplies the bias for the ic, the low side gate drivers, and the external boot circuitry for the high side gate drivers. the ic may be powered directly from a single 5v (10%) supply at this pin. when used as a 5v supply input, this pin must be externally conected to v in . the vcc_5v pin must be always decoupled to power ground with a minimum of 4.7 f ceramic capacitor, placed very close to the pin. sync - this pin may be used to synchronize two or more isl6402a controllers. this pin requires a 1k resistor to ground if used; connect direct ly to vcc_5v if not used. ss1, ss2 - these pins provide a soft-start function for their respective pwm controllers. when the chip is enabled, the regulated 5 a pull-up current source charges the capacitor connected from this pin to ground. the error amplifier reference voltage ramps from 0 to 0.8v while the voltage on the soft-start pin ramps from 0 to 0.8v. sd1 , sd2 - these pins provide an enable/disable function for their respective pwm output. the output is enabled when this pin is floating or pulled high, and disabled when the pin is pulled low. gate3 - this pin is the open drain output of the linear regulator controller. ocset2, ocset1 - a resistor from this pin to ground sets the overcurrent threshold for the respective pwm. functional description general description the isl6402a integrates control circuits for two synchronous buck converters and one linear controller. the two synchronous bucks operate ou t of phase to substantially reduce the input ripple and thus reduce the input filter requirements. the chip has four control lines (ss1, sd1 , ss2, and sd2 ), which provide independent control for each of the synchronous buck outputs. the buck pwm controllers employ a free-running frequency of 1.4mhz. the current mode control scheme with an input voltage feed-forward ramp input to the modulator provides excellent rejection of input voltage variations and provides simplified loop compensations. the linear controller can drive either a pnp or pfet to provide ultra low-dropout regulation with programmable voltages. internal 5v linear regulator (vcc_5v) all isl6402a functions are internally powered from an on- chip, low dropout 5v regulator. the maximum regulator input voltage is 24v. bypass the regulator?s output (vcc_5v) with a 4.7f capacitor to ground. the dropout voltage for this ldo is typically 600mv, so when vcc_5v is greater then 5.6v, vcc_5v is typically 5v. the isl6402a also employs an undervoltage lockout circuit that disables both regulators when vcc_5v falls below 4.4v. the internal ldo can source ov er 60ma to supply the ic, power the low side gate drivers, charge the external boot capacitor and supply small external loads. when driving large fets especially at 1.4mhz frequency, little or no regulator current may be available for external loads. isl6402a
11 for example, a single large fe t with 15nc total gate charge requires 15nc x 1.4mhz = 21ma. also, at higher input voltages with larger fets, the power dissipation across the internal 5v will increase. excessive dissipation across this regulator must be avoided to prevent junction temperature rise. larger fets can be used with 5v 10% input applications. the thermal overlo ad protection circuit will be triggered if the vcc_5v output is short circuited. connect vcc_5v to vin for 5v 10% input applications. soft-start operation when soft-start is initiated, the voltage on the ss pin of the enabled pwm channels starts to ramp gradually, due to the 5 a current sourced into the external capacitor. the output voltage follows the soft-start voltage. when the ss pin voltage reaches 0.8v, the output voltage of the enabled pwm channel reaches the regulation point, and the soft-start pin voltage continues to rise. at this point the pgood and fault circuitry is enabled. this completes the soft-start sequence. any further rise of ss pin voltage does not affect the output voltage. by varying the values of the soft-start capacitors, it is possible to provide sequencing of the main outputs at start-up. the soft-start time can be obtained from the following equation: the soft-start capacitors can be chosen to provide startup tracking for the two pwm outputs. this can be achieved by choosing the soft-start capacito rs such that the soft-start capacitor ration equals the respective pwm output voltage ratio. for example, if i use pwm1 = 1.2v and pwm2 = 3.3v then the soft-start capacitor ration should be, c ss1 /c ss1 = 1.2/3.3 = 0.364. figure 14 below shows that soft-start waveform with c ss1 = 0.01f and c ss2 = 0.027f. output voltage programming a resistive divider from the out put to ground sets the output voltage of either pwm channel. the center point of the divider shall be connected to fbx pin. the output voltage value is determined by the following equation. where r1 is the top resistor of the feedback divider network and r2 is the resistor connected from fbx to ground. out-of-phase operation the two pwm controllers in the isl6402a operate 180 o out- of-phase to reduce input ripple current. this reduces the input capacitor ripple current requirements, reduces power supply-induced noise, and impr oves emi. this effectively helps to lower component cost, save board space and reduce emi. dual pwms typically operate in-phase and turn on both upper fets at the same time. the input capacitor must then support the instantaneous current requirements of both controllers simultaneously, resulting in increased ripple voltage and current. the higher rms ripple current lowers the efficiency due to the power loss associated with the esr of the input capacitor. this typically requires more low-esr capacitors in parallel to minimize the input voltage ripple and esr-related losses, or to meet the required ripple current rating. with dual synchronized out-of-phase operation, the high- side mosfets of the isl6402a turn on 180 o out-of-phase. the instantaneous input current peaks of both regulators no longer overlap, resulting in reduced rms ripple current and input voltage ripple. this reduces the required input capacitor ripple current ra ting, allowing fewer or less expensive capacitors, and reducing the shielding requirements for emi. the typi cal operating curves show the synchronized 180 degree out-of-phase operation. t soft 0.8v c ss 5 a ----------- ?? ?? = figure 13. soft-start operation vcc_5v 1v/div ss1 1v/div v out1 1v/div figure 14. pwm1 and pwm2 output tracking during startup v out1 1v/div v out2 1v/div v outx 0.8v r1 r2 + r2 ---------------------- ?? ?? = isl6402a
12 input voltage range the isl6402a is designed to operate from input supplies ranging from 4.5v to 24v. however, the input voltage range can be effectively limited by the available maximum duty cycle (d max = 71%). where, vd1 = sum of the parasitic voltage drops in the inductor discharge path, including the lower fet, inductor and pc board. vd2 = sum of the voltage drops in the charging path, including the upper fet, inductor and pc board resistances. the maximum input voltage and minimum output voltage is limited by the minimum on-time (t on(min) ). where, t on(min) = 30ns gate control logic the gate control logic translates generated pwm signals into gate drive signals providin g amplification, level shifting and shoot-through protection. the gate drivers have some circuitry that helps optimize the ic?s performance over a wide range of operational condit ions. as mosfet switching times can vary dramatically fr om type to type and with input voltage, the gate control logic provides adaptive dead time by monitoring real gate waveforms of both the upper and the lower mosfets. shoot-through control logic provides a 20ns deadtime to ensure that both the upper and lower mosfets will not turn on simultaneously and cause a shoot- through condition. gate drivers the low-side gate driver is supplied from vcc_5v and provides a peak sink/source current of 400ma. the high- side gate driver is also capable of 400ma current. gate-drive voltages for the upper n-channel mosfet are generated by the flying capacitor boot circuit. a boot capacitor connected from the boot pin to the phase node provides power to the high side mosfet driver. to limit the peak current in the ic, an external resistor may be placed between the ugate pin and the gate of the external mosfet. this small series resistor also damps any oscillations caused by the re sonant tank of the parasitic inductances in the traces of the board and the fet?s input capacitance. at start-up the low-side mosfet turns on and forces phase to ground in order to c harge the boot capacitor to 5v. after the low-side mosfet turns off, the high-side mosfet is turned on by closing an internal switch between boot and ugate. this provides the necessary gate-to- source voltage to turn on t he upper mosfet, an action that boosts the 5v gate drive signal above vin. the current required to drive the upper mosfet is drawn from the internal 5v regulator. protection circuits the converter output is mo nitored and protected against overload, short circuit and undervoltage conditions. a sustained overload on the outpu t sets the pgood low and initiates hiccup mode. overcurrent protection cycle by cycle current limiting scheme is implemented as below. both pwm controllers use the lower mosfet?s on- resistance, r ds(on) , to monitor the current in the converter. the sensed voltage drop is compared with a threshold set by a resistor connected from the ocsetx pin to ground. where, i oc is the desired overcurrent protection threshold, and r cs is a value of the current sense resistor connected to the isenx pin. if the lowe r mosfet current exceeds the over-current threshold, a pulse skipping circuit is activated. figure 16 shows the inductor cu rrent, output voltage, and the phase node voltage just as an overcurrent trip occurs. the upper mosfet will not be turned on as long as the sensed current is higher than the threshold value. this limits the current supplied by the dc voltage source. if an overcurrent is detected for 2 consecutive cl ock cycles then the ic enters a hiccup mode by turning off the gate drivers and entering into soft-start. the ic will cycle 2 times through soft-start before trying to restart. the ic will continue to cycle through soft-start until the overcurrent condition is removed. figure 17 shows this behavior. v in min () v out v d1 + 0.71 -------------------------------- ?? ?? v d2 v d1 ? + = v in max () v out t on min () 1.4mhz --------------------------------------------------- - boot ugate phase vcc_5v vin isl6402a figure 15. r ocset 7 () r cs () i oc () r ds on () () ------------------------------------------ - = isl6402a
13 because of the nature of this current sensing technique, and to accommodate a wide range of r ds(on) variations, the value of the overcurrent threshold should represent an overload current about 150% to 180% of the maximum operating current. if more accurate current protection is desired, place a current sense resistor in series with the lower mosfet source. over-temperature protection the ic incorporates an over-t emperature protection circuit that shuts the ic down when a die temperature of 150c is reached. normal operation resumes when the die temperatures drops below 130c through the initiation of a full soft-start cycle. implementing synchronization the sync pin may be used to synchronize two or more controllers. when the sync pins of two controllers are connected together, one controller becomes the master and the other controller synchronize s to the master. a pull-down resistor is required and must be sized to provide a low enough time constant to pass the sync pulse. connect this pin to vcc_5v if not used. figure 18 shows the sync pin waveform operating at 4 times the switching frequency. feedback loop compensation to reduce the number of external components and to simplify the process of determining compensation components, both pwm controllers have internally compensated error amplifiers. to make internal compensation possible seve ral design measures were taken. first, the ramp signal applied to the pwm comparator is proportional to the input volt age provided via the vin pin. this keeps the modulator gain constant with variation in the input voltage. second, the load current proportional signal is derived from the voltage drop across the lower mosfet during the pwm time interval and is subtracted from the amplified error signal on the comparator input. this creates an internal current control lo op. the resistor connected to the isen pin sets the gain in the current feedback loop. the following expression estimates the required value of the current sense resistor depending on the maximum operating load current and the value of the mosfet?s r ds(on) . choosing r cs to provide 32a of current to the current sample and hold circuitry will ensure accurate overcurrent detection. v out2 2v/div phase2 10v/div i l 2v/div figure 16. overcurrent trip waveforms v out2 2v/div ss2 2v/div i out2 2v/div figure 17. overcurrent continuous hiccup mode waveforms figure 18. sync waveform sync 1v/div r cs i max () r dson ) () 32 a --------------------------------------------- isl6402a
14 due to the current loop feedback, the modulator has a single pole response with -20 db slope at a frequency determined by the load. where r o is load resistance and c o is load capacitance. for this type of modulator, a type 2 compensation circuit is usually sufficient. figure 19 shows a type 2 amplifier and it?s response along with the responses of the cu rrent mode modulator and the converter. the type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a flat gain region at frequencies in between the zero and the pole. the zero frequency, the amplifier high-frequency gain, and the modulator gain are chosen to satisfy most typical applications. the crossover frequency will appear at the point where the modulator att enuation equals the amplifier high frequency gain . the only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero fr equency. with this type of compensation plenty of phase ma rgin is easily achieved due to zero-pole pair phase ?boost?. conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. in this case, the esr zero placed within the 10khz to 50khz range gives some additional phase ?boost?. some phase boost can also be achieved by connecting capacitor c z in parallel with the upper resistor r1 of the divider that sets the output voltage value. please refer to the output inductor and capacitor selection sections for further details. linear regulator the linear regulator controller is a transconductance amplifier with a nominal gain of 2 a/v. the n-channel mosfet output device can sink a minimum of 50ma. the reference voltage is 0.8v. with zero volts differential at its input, the controller sinks 21ma of current. an external pnp transistor or pfet pass elem ent can be used. the dominant pole for the loop can be placed at the base of the pnp (or gate of the pfet), as a capacitor from emitter to base (source to gate of a pfet). bett er load transient response is achieved however, if the domin ant pole is placed at the output, with a capacitor to ground at the output of the regulator. under no-load conditions, leakage currents from the pass transistors supply the output capacitors, even when the transistor is off. generally this is not a problem since the feedback resistor drains the excess charge. however, charge may build up on the output capacitor making v ldo rise above its set point. care must be taken to insure that the feedback resistor?s current exceeds the pass transistor?s leakage current over the entire temperature range. the linear regulator output can be supplied by the output of one of the pwms. when using a pfet, the output of the linear will track the pwm supply after the pwm output rises to a voltage greater than the threshold of the pfet pass device. the voltage differential between the pwm and the linear output will be the load current times the r ds(on) . figure 20 shows the linear regulator (2.5v) startup waveform and the pwm (3.3v) startup waveform. f po 1 2 r o c o ?? -------------------------------- - , = f z 1 2 r 2 c 1 ?? ------------------------------ - 10khz == f p 1 2 r 1 c 2 ?? ------------------------------ - 600khz == figure 19. feedback loop compensation r1 r2 c1 c2 f po f z f p f c modulator ea converter type 2 ea g ea =13db g m =15.5db figure 20. linear regulator startup waveform v out2 1v/div v out3 1v/div isl6402a
15 base-drive noise reduction the high-impedance base driver is susceptible to system noise, especially when the linear regulator is lightly loaded. capacitively coupled switching noise or inductively coupled emi onto the base drive causes fluctuations in the base current, which appear as noise on the linear regulator?s output. keep the base drive trac es away from the step-down converter, and as short as possible, to minimize noise coupling. a resistor in series with the gate drivers reduces the switching noise generated by pwm. additionally, a bypass capacitor may be placed across the base-to-emitter resistor. this bypass capacitor, in addition to the transistor?s input capacitor, could bring in second pole that will de- stabilize the linear regulator. therefore, the stability requirements determine the maximum base-to-emitter capacitance. layout guidelines careful attention to layout requirements is necessary for successful implementation of an isl6402a based dc-dc converter. the isl6402a switches at a very high frequency and therefore the switching times are very short. at these switching frequencies, even the shortest trace has significant impedance. also the peak gate drive current rises significantly in extremely short time. transition speed of the current from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, generate emi, increase device over voltage stress and ringing. careful component selection and proper pc board layout minimizes the magnitude of these voltage spikes. there are two sets of crit ical components in a dc-dc converter using the isl6402a; the switching power components and the small signal components. the switching power components are the most critical from a layout point of view because they switch a large amount of energy so they tend to generat e a large amount of noise. the critical small signal com ponents are those connected to sensitive nodes or those supplyi ng critical bias currents. a multi-layer printed circuit board is recommended. layout considerations 1. the input capacitors, upper fet, lower fet, inductor and output capacitor, should be placed first. isolate these power components on the topside of the board with their ground terminals adjacent to one another. place the input high frequency decoupling ceramic capacitor very close to the mosfets. 2. use separate ground planes for power ground and small signal ground. connect the sgnd and pgnd together close of the ic. do not conne ct them together anywhere else. 3. the loop formed by input capacitor, the top fet and the bottom fet must be kept as small as possible. 4. insure the current paths from the input capacitor to the mosfet; to the output inductor and output capacitor are as short as possible with maximum allowable trace widths. 5. place the pwm controller ic close to lower fet. the lgate connection should be short and wide. the ic can be best placed over a quiet ground area. avoid switching ground loop current in this area. 6. place vcc_5v bypass capacitor very close to vcc_5v pin of the ic and connect its ground to the pgnd plane. 7. place the gate drive components boot diode and boot capacitors together near controller ic. 8. the output capacitors should be placed as close to the load as possible. use short wide copper regions to connect output capacitors to load to avoid inductance and resistances. 9. use copper filled polygons or wide but short trace to connect junction of upper fet, lower fet and output inductor. also keep the phase node connection to the ic short. do not unnecessarily oversize the copper islands for phase node. since the phase nodes are subjected to very high dv/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise. 10. route all high speed switching nodes away from the control circuitry. 11. create a separate small analog ground plane near the ic. connect sgnd pin to this plane. all small signal grounding paths including feedback resistors, current limit setting resistors and sy nc/sdx pull down resistors should be connected to this sgnd plane. 12. ensure the feedback connection to output capacitor is short and direct. component selection guidelines mosfet considerations the logic level mosfets are chosen for optimum efficiency given the potentially wide in put voltage range and output power requirements. two n-channel mosfets are used in each of the synchronous-rectified buck converters for the pwm1 and pwm2 outputs. these mosfets should be 0.79 0.8 0.82 0.83 0.85 0 40 60 feedback voltage (v) error amplifier sink 20 50 30 10 current (ma) 0.81 0.84 figure 21. linear controller gain isl6402a
16 selected based upon r ds(on) , gate supply requirements, and thermal management considerations. the power dissipation includes two loss components; conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty cycle (see the following equations). the conduction losses are the main component of power dissipation for the lower mosfets. only the upper mosfet has significant switching losses, since the lower device turns on and off into near zero voltage. the equations assume linear voltage-current transitio ns and do not model power loss due to the reverse-recove ry of the lower mosfet?s body diode. a large gate-charge increases the switching time, t sw , which increases the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at hi gh ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. output capacitor selection the output capacitors for each output have unique requirements. in general, the output capacitors should be selected to meet the dynam ic regulation requirements including ripple voltage and load transients. selection of output capacitors is also de pendent on the output inductor, so some inductor analysis is required to select the output capacitors. one of the parameters limiting the converter?s response to a load transient is the time required for the inductor current to slew to its new level. the isl6402a will provide either 0% or 71% duty cycle in response to a load transient. the response time is the time interval required to slew the inductor current from an initial current value to the load current level. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s ). minimizing the response time can minimize the output ca pacitance required. also, if the load transient rise time is slower than the inductor response time, as in a hard drive or cd drive, it reduces the requirement on the output capacitor. the maximum capacitor value required to provide the full, rising step, transient load current during the response time of the inductor is: where, c out is the output capacitor(s) required, l o is the output inductor, i tran is the transient load current step, v in is the input voltage, v o is output voltage, and dv out is the drop in output voltage allowed during the load transient. high frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (equivalent series resistance) and voltage rating requirements as well as actual capacitance requirements. the output voltage ripple is due to the inductor ripple current and the esr of the output capacitors as defined by: where, i l is calculated in the inductor selection section. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load circuitry for specific decoupling requirements. use only specialized low-es r capacitors intended for switching-regulator applications at 1.4mhz for the bulk capacitors. in most cases, mult iple small-case electrolytic capacitors perform better than a single large-case capacitor. the stability requirement on the selection of the output capacitor is that the ?esr zero?, f z , be between 2khz and 50khz. this range is set by an internal, single compensation zero at 10khz. the esr zero can be a factor of five on either side of the internal zero and still contribute to increased phase margin of the co ntrol loop. therefore, in conclusion, the output capaci tors must meet three criteria: 1. they must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient, 2. the esr must be sufficiently low to meet the desired output voltage ripple due to the output inductor current, and 3. the esr zero should be placed in a rather large range, to provide additional phase margin. the recommended output capacitor value for the isl6402a is between 150 f to 680 f, to meet stability criteria with external compensation. use of low esr ceramic capacitors is possible but would take more rigorous loop analysis to ensure stability. p upper i o 2 () r ds on () () v out () v in --------------------------------------------------------------- i o () v in () t sw () f sw () 2 ----------------------------------------------------------- - + = p lower i o 2 () r ds on () () v in v out ? () v in ------------------------------------------------------------------------------ - = c out l o () i tran () 2 2v in v o ? () dv out () ---------------------------------------------------------- - = v ripple ? i l esr () = c out 1 2 esr () f z () ------------------------------------ - = isl6402a
17 output inductor selection the pwm converters require output inductors. the output inductor is selected to meet the output voltage ripple requirements. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current and output capacitor(s) esr. the ripple voltage expression is given in the capacitor selection section and the ripple current is approximated by the following equation: for the isl6402a, use inductor values between 1 h to 3.3 h. input capacitor selection the important parameters for the bulk input capacitor(s) are the voltage rating and the rms current rating. for reliable operation, select bulk input capacitors with voltage and current ratings above the maxi mum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a conservative guideline. the ac rms input current varies with the load. the total rms current supplied by the input capacitance is: where, dc is duty cycle of the respective pwm. depending on the specifics of the input power and its impedance, most (or all) of this current is supplied by the input capacitor(s). figure 22 shows the advantage of having the pwm converters operating out of phase. if the converters were operating in phase, the combined rms current would be the algebraic su m, which is a much larger value as shown. the combined out-of-phase current is the square root of the sum of the square of the individual reflected currents and is signif icantly less than the combined in-phase current. use a mix of input bypass capaci tors to control the voltage ripple across the mosfets. us e ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capa citors can be placed very close to the upper mosfet to suppress the voltage induced in the parasitic circuit impedances. for board designs that allow through-hole components, the sanyo os-con? series offer low esr and good temperature performance. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge- current at power-up. the tps series available from avx is surge current tested. ? i l v in v out ? () v out () f s () l () v in () --------------------------------------------------------- - = i rms i rms1 2 i rms2 2 + = i rmsx dc dc 2 ? = figure 22. input rms current vs load 12345 3.3v and 5v load current input rms current 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 in phase out of phase 5v 3.3v isl6402a
18 isl6402a quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l28.5x5 28 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhd-1 issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5,8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7,8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7,8 e 0.50 bsc - k0.25 - - - l 0.50 0.60 0.75 8 l1 - - 0.15 10 n282 nd 7 3 ne 8 7 3 p- -0.609 --129 rev. 0 02/03 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
19 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com isl6402a thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ae, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m28.173 28 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.378 0.386 9.60 9.80 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 6/98

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